1) Field
Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of silicon etch for trench sidewall smoothing.
2) Description of Related Art
Demand for smaller and lighter electronic devices with higher performance and increased features is driving the adoption of three dimensional (3D) integrated circuits (ICs) designed with through silicon vias (TSVs). TSVs are electrical connections which pass through layers of a semiconductor wafer. Despite the increased interest in TSVs, adoption of TSVs has been slowed due to, for example, high costs and challenges associated with high volume manufacturing. One such challenge includes creating TSV trenches with smooth sidewalls. Trenches with smooth sidewalls are generally more robust and can be effectively filled with materials such as dielectrics and metals. In contrast, trenches with rough sidewalls (e.g., scalloped sidewalls) can result in ineffective filling, leading to reduced yield and long-term device reliability problems. Unfortunately, existing methods of TSV etching create trenches with rough sidewalls, and/or are impractical for high volume manufacturing. Another factor influencing adoption of TSVs includes the cost of performing plasma etching, which is influenced by, for example, the overall silicon etch rate.